Design of data - collecting device with low power - consumption 低功耗數(shù)據(jù)采集裝置的設(shè)計(jì)
Through this 1c design project , we realize the main function of the data - collecting device and will bring great advantage to produce the data - collecting 1c . based on such research , we will speed the development of the amr system 通過此次設(shè)計(jì),用fpga方式實(shí)現(xiàn)了現(xiàn)有抄表器產(chǎn)品的基本功能,為將來進(jìn)一步開發(fā)研制抄表芯片積累了經(jīng)驗(yàn),奠定了基礎(chǔ)。
Comparing the different design method of the asic , we decide to realize our design through fpga . then , we analyze the main function of the data - collecting device which include pulse signal collecting , counting the pulse according to different time , display , storage , communicating , remote control and so on . according to some technology rules , we design the asic through verilog hdl 根據(jù)抄表器所需實(shí)現(xiàn)的表計(jì)脈沖數(shù)據(jù)采集、計(jì)量數(shù)據(jù)的分時(shí)段管理、顯示控制、數(shù)據(jù)存儲(chǔ)及通訊管理、遠(yuǎn)程控制的管理等功能,結(jié)合現(xiàn)有的一些技術(shù)規(guī)范,用veriloghdl實(shí)現(xiàn)抄表器的硬件電路描述。
Data - collecting device is one of the most important parts of this system . in this thesis , we advance a new method based on the asic technology to realize the main function of the data - collecting device in the market now . at first , we introduce the advantage of designing the device through asic technology 文章介紹了用專用集成電路方法設(shè)計(jì)抄表器電路的優(yōu)點(diǎn),并對專用集成電路的各種設(shè)計(jì)方法作了比較,結(jié)合本課題的時(shí)間緊、費(fèi)用低、需要取得階段性成果的特點(diǎn),提出了用fpga方式來實(shí)現(xiàn)抄表器的asic設(shè)計(jì)。